[hpsdr] Horton LO

[Alex]

PICTURES, PICTURES, PICTURES.

Plus how is this going to fill the bill for the VHF+ world. Speaking as one who is only interested in the VHF+ applications.
(I will tolerate the HF if it will help reach the end goal).

Alex, N3NP

----- Original Message ----
From: Christopher T. Day <CTDay at lbl.gov>
To: Robert McGwier <rwmcgwier at comcast.net>; Lyle Johnson <kk7p at wavecable.com>
Cc: Richard M. Hambly <rick at cnssys.com>; hpsdr at hpsdr.org
Sent: Friday, June 16, 2006 5:06:28 PM
Subject: Re: [hpsdr] Horton LO

***** High Performance Software Defined Radio Discussion List *****

Sorry, I'm only part way through this thread and panting to keep up. A
picture would be nice.

One bit here is partitioning. Is this LO really part of Horton or is it
the reference that we want Gibraltar to produce? It sounds like we have:

1) 500 MHz very low phase noise VCO. A Valpey-Fisher device is on the
table.
2) Quad divide-by-four chain to get signals to feed Horton's QSD. =>
Horton is listening at 125MHz(?).
3) Continued quad(?) divider chain to get down to lock points spaced
closely enough for software frequency shift of the received signals to
be used for fine tuning between the lock points.
4) A GPS disciplining chain to actually lock the VCO to the lock point.
5) For total coherence, there also should be a chain to drive the
ADC/DACs.

How far off is this picture? 

For 2), it feels to me that a frequency selection is missing - if Horton
is running at 125MHz, how do I choose to hear 7.020 MHz?

For 3), why does it have to be a quad divider?

If this is at all right, the central role of this LO seems to me to
drive much of it off to Gibraltar. Maybe some of the divider chains go
on Horton?

Sorry if this is obvious to you all, but I'm a little lost.


    Chris - AE6VK


-----Original Message-----
From: Robert McGwier [mailto:rwmcgwier at comcast.net] 
Sent: Friday, June 16, 2006 10:51 AM
To: Lyle Johnson
Cc: pvharman at arach.net.au; Christopher T. Day; Richard M. Hambly;
hpsdr at hpsdr.org
Subject: Re: [hpsdr] Horton LO

It will be exceedingly important for phase coherent processing that we 
use the same clock to derive other clocks.   So for example,  Horton 
needs to hear the minimum Who by having this same clock have a divider 
that will produce a 200 kHz or N*200 Khz clock for the AKM5394A.  This 
will make  the entire system phase coherent with a dynamic range, and 
other parameters never before achieved to my knowledge.  We are 
basically talking a serious revolution with this.  I would suggest 
strongly in addition that we make provision for driving Mercury from the

125 MHz clock (giving up10 MHz of bandwidth) to, once again,  get a 
phase coherent system.  NISSSHH.

The Phil's have hit a home run here.

Bob




Lyle Johnson wrote:
>> If we take the 500 MHz high quality oscillators and do a johnson 
>> counter to produce four signals at 125 MHz to drive the capacitors in

>> the QSD,  we can then feed each of the 125 MHz signals into four 
>> equal length divider chains.  With 16 bit dividers,   we get 2.5 KHz 
>> resolution.  If we find we cannot put the 16 bit counters in a CPLD,
>
> CPLD or FPGA creating four instances of a 16-bit programmable divider 
> with 50% output duty cycle is easy.
>
> What we need is an FPGA or CPLD with four "zero delay, high drive" 
> clock lines inside the part.  I suspect the phase noise we'll get from

> the division process switching threshold uncertainties will be fairly 
> small, and adequate for our purposes.
>
> The Max II device from Altera for example, has speed grades rated to 
> clock at 300 MHz and has exactly four global clock lines.  The 
> smallest device, like we're using in Janus, has 240 FPGA logic 
> elements, so we'd have 60 for each programmable divider.  We'd need 
> fewer, giving us some to use as the input program register to steer 
> the dividers.  $8 or so for the fast parts.
>
> The smallest Cyclone II device, like Phil is using in Ozymandias, has 
> 8 global networks, 4608 logic elements, and is available in speed 
> grades to 260 MHz.  The EP2C5T144C7() is only $15.30 in singles.
>
> I think if the jitter in these parts is acceptable, all we need is the

> VP oscillator and the 500 MHz Johnson counter.  The jitter properties 
> of the divider will be important, but of course that'll be divided 
> down/averaged by the 16-bit programmable counter.  Need to find the 
> right way to implement that counter...
>
> 73,
>
> Lyle KK7P
>
>
>
>


-- 
AMSAT VP Engineering. Member: ARRL, AMSAT-DL, TAPR, Packrats,
NJQRP/AMQRP, QRP ARCI, QCWA, FRC. ARRL SDR Wrk Grp Chairman
Laziness is the number one inspiration for ingenuity.  Guilty as
charged!


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