[hpsdr] Horton LO

[Philip Covington]

On 6/16/06, Phil Harman <pvharman at arach.net.au> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> Ok - I worked through Phil C's math last night and it looks fine to me. I
> will draw up a block diagram and the divider list today and post to the
> forum.
>
> Phil...VK6APH

Hi Phil,

Take a look at the Minicircuits ROS-2150VW.  Its tuning range is
970-2150 and the phase noise isn't too horrible.  This with a National
PLL tuning in coarse steps might do it.  We'd have to divide down into
a range where the CPLD or FPGA would handle the final divider chain.

73 de Phil N8VB

 1150513834.0