[hpsdr] Mercury - Design assistance required

[Phil Harman]

Hi Willi,

I'll follow that up .  I have had one breakthrough tonight.  The problems I 
have been having with spurs as you approach 0Hz turns out to be the fact 
that the ADC input circuit was picking up the digital outputs.  Not really 
surprising given the breadboard that I am using. Anyway by using the in 
built digital output randomizer in the LT2208 and its inverse in the FPGA I 
have almost completely eliminated all these spurs.

The spectrum is looking very much better now.

73's Phil....VK6APH


----- Original Message ----- 
From: "W.J.Kinowsky" <dg8caa at kinowsky.de>
To: <pvharman at arach.net.au>; <hpsdr at hpsdr.org>
Sent: Thursday, June 22, 2006 5:29 PM
Subject: AW: [hpsdr] Mercury - Design assistance required


Phil,

There is a software from Analog Devices called
"SoftCell Filter Design Software". Maybe it helps.

Regards
Willi DG8CAA


> -----Ursprüngliche Nachricht-----
> Von: hpsdr-bounces at hpsdr.org [mailto:hpsdr-bounces at hpsdr.org]
> Im Auftrag von pvharman at arach.net.au
> Gesendet: Donnerstag, 22. Juni 2006 07:31
> An: hpsdr at hpsdr.org
> Betreff: [hpsdr] Mercury - Design assistance required
>
> ***** High Performance Software Defined Radio Discussion List *****
>
> Mercury - Design assistance required
>
>
> Whilst I have made good progress with interfacing the LT2208
> 130MSPS 16 bit ADC to the Xylo FPGA board and then to
> PowerSDR via USB 2,  I have run in a few design issues.
>
> The data from the LT2208 is 16 bits wide and is clocked at
> 100MHz.  This data is fed into the Cyclone FPGA on the Xylo
> board on the positive edge of the clock and feeds a CIC
> decimating filter.  The output of the CIC  is  processed by
> the FGPA, in the same manner as the Janus ADC data was,  and
> fed to the FX2
> USB2 chip where it makes it way to PowerSDR.
>
> The section I am having a problem with is the design of the
> CIC filter.  I have access to Matlab and I can design
> filters using that, convert the design into  Verilog and then
> load and run that in the Xylo.
>
> I don't quite understand what parameters I should be using to
> design the CIC filter.  If we want a bandscope bandwidth of
> +/-96kHz then I need to decimate the 100MHz ADC data by
> ~512.  So far I have been  doing this amount of decimation in
> the CIC filter and using Matlab to design the order of the
> filter - this is usually between 7 and 9  - to reduce
> aliasing products by 100dB.
>
> Whilst I can implement this in the FPGA the level of spurious
> signals is totally unacceptable - particularly as one tunes
> towards 0Hz.
>
> Yesterday I came across a design document for the AD6620 DDC chip
>
> <
> http://www.analog.com/UploadedFiles/Data_Sheets/180387430AD662
> 0_a.pdf >
>
> Using their design guide indicates that I should be using a
> second order CIC filter with a  decimation factor of  3
> followed by a second, fifth order, CIC filter also with a
> decimation factor or 3. Very different values than I have
> been using to date!
>
> Does any one have experience in the design of decimating CIC
> filters or a reference that explains how to design them in
> more detail.
>
> 73's Phil...VK6APH
>
>
>
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