[hpsdr] Mercury – Design assistance required

[Eric Blossom]

On Thu, Jun 22, 2006 at 01:30:51PM +0800, pvharman at arach.net.au wrote:
> 
> Mercury Design assistance required
> 
> Whilst I have made good progress with interfacing the LT2208  130MSPS 16 bit 
> ADC to the Xylo FPGA board and then to PowerSDR via USB 2,  I have run in a 
> few design issues. 
> 
> The section I am having a problem with is the design of the CIC filter.  I 
> have access to Matlab and I can design  filters using that, convert the design 
> into Verilog and then load and run that in the Xylo. 

Have you looked at the usrp/fpga/sdr_lib/cic_decim.v in the USRP fpga
code?  By default it implements a 4th order CIC decimator, with a maximum
decimation factor for 256, however the verilog is parameterized:

    module cic_decim
      ( clock,reset,enable,rate,strobe_in,strobe_out,signal_in,signal_out);
       parameter bw = 16;
       parameter N = 4;
       parameter log2_of_max_rate = 8;
       parameter maxbitgain = N * log2_of_max_rate;
   

> I don't quite understand what parameters I should be using to design the CIC 
> filter.  If we want a bandscope bandwidth of +/-96kHz then I need to decimate 
> the 100MHz ADC data by  ~512.  So far I have been  doing this amount of  
> decimation in the CIC filter and using Matlab to design the order of the 
> filter – this is usually between 7 and 9  - to reduce aliasing products by 
> 100dB. 

Follow the CIC decimator by one or two halfband filters and life will
be good.  You'll have a nice flat pass band with good rejection of
aliases.

For example to get from 100MHz to 96 KHz, you need to decimate by
about 1042.  Call is 1024, and resample if required in s/w.
Decimate by 256 in the CIC, then follow that by two halfbands,
each of which decimates by 2.

You could do this by decimating by 512 in the CIC, then one halfband,
but life will be better with two halfbands.

FYI, here are 16-bit fixed point taps for a 31-tap halfband.  Divide by
32768 to get floating point:

	-16
	0
	74
	0
	-254
	0
	669
	0
	-1468
	0
	2950
	0
	-6158
	0
	20585
	32768
	20585
	0
	-6158
	0
	2950
	0
	-1468
	0
	669
	0
	-254
	0
	74
	0
	-16

> Whilst I can implement this in the FPGA the level of spurious signals is 
> totally unacceptable – particularly as one tunes towards 0Hz. 
> 
> Does any one have experience in the design of decimating CIC filters or a 
> reference that explains how to design them in more detail.

There's not much to designing them.  There aren't that many knobs to
twist.  The shape is determined by the order.  The required width of
the guts is determined by the maximum decimation factor and order.
See pretty much any DSP and/or digital comms book.  Sorry, I'm away
from my library and can't get you a more specific recommendation.

73 Eric K7GNU

 1150996230.0