[hpsdr] Lionheart to Atlas bus signals...

[Philip Covington]

Hi group,

I am somewhat concerned that we are getting too specific in the
definition of certain signals from the Lionheart to the Atlas bus. 
Would it not be a better idea to keep that definition more generic? -
we have a FPGA so the actual function of those signals can be pretty
much redefined at any time.

I think as long as we bring the XBUS and YBUS lines to the FPGA we
will be in good shape.  Let's not define certain I/O lines out of the
Lionheart as I2S, I2C, SPI, etc... quite yet.

I think we the I2C and SPI buses should come from the FPGA also and
not the FX2 as far as the Atlas is concerned.  The FX2 can have it's
own private I2C bus (maybe also brought out to a header) to talk to
its serial EEPROM (PLEASE add this as Eric B. suggested - we need our
own VID/PID/DID).  [We can have the FX2 optionally start from this
EEPROM instead of having to upload the firmware over the USB.]  By
having the FPGA do the I2C and SPI we can defer the definition of
which actual lines on the Altas bus until later.

I am in complete agreement with Eric B. that all possible pins of the
FX2 should be connected to the FPGA even if this means going to the
next device up to get the I/O count we need.  If you think of the FPGA
as a kind of wirewrap breadboard you will also see the importance of
this.  Adding some headers on the Lionheart to bring out extra I/O
from the FPGA is also a good idea for future expansion.

73 de Phil N8VB

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