[hpsdr] [ATLAS] - proposed physical bus/pcb design 03March2006

[Philip Covington]

On 3/3/06, Lyle Johnson <kk7p at wavecable.com> wrote:
> Hello Phil!
>
> > For those interested, I'd appreciate if you'd please take a look at
> > the documents and make questions/comments.
>
> In general I like what I see.
>
> A suggestion: I would like to see some small subset of a bus, maybe one
> of the X buses so it will be supported with a 64-pin DIN connector - be
> changes such that it is daisy chained between slots.  This makes it much
> easier to set up things like JTAG chains, slot-based priority interrupt
> schemes, and the like.
>
> Foe example Bus XC[0:7] could be broken into XC[0:3] as at present.  The
> present wiring of XC[4:7] going to pins A[22:25] might be rewired like this:
>
> J1    J2    J3    J4    J5    J6
> A22---A22   A22---A22   A22---A22
> A23   A23---A23   A23---A23   A23--- to J1 A23 or n/c
> A24---A24   A24---A24   A24---A24
> A25   A25---A25   A25---A25   A25--- to J1 A25 or n/c
>
> I realize this can be done by cutting on the board, but the X traces are
> inner layer and the Y traces are only on the 96-pin connectors.
>
> Alternately, this could be done on the Y traces and just accept the fact
> that this is a "high end" feature and thus only supported on 96-pin
> boards.  This restriction, however, means that any intervening boards
> must also be 96-pin, which limits it usefulness.

Hi Lyle,

Actually, I had already made a provision for this possibility.  The
XBUS (on the bottom of the board), and the YBUS (between the two plane
layers) are routed between the J7-J20 pins on their respective layers.
  The actual short traces (0.200" long) from the J7-J20 headers to the
slot connectors (J1-J6) are all horizontally on the bottom layer of
the board so you have full access to both the X and Y lines.

I will post a bottom layer trace picture and the gerbers (for those
who want to see them in a gerber viewer program) later today when I
get a chance.

73 de Phil N8VB

 1141410148.0