[hpsdr] [ATLAS] - proposed physical bus/pcb design 03March2006

[Philip Covington]

On 3/3/06, Lyle Johnson <kk7p at wavecable.com> wrote:
> Hello Phil!
>
> >>> A suggestion: I would like to see some small subset of a bus, maybe one
> >>> of the X buses so it will be supported with a 64-pin DIN connector - be
> >>> changes such that it is daisy chained between slots.  This makes it much
> >>> easier to set up things like JTAG chains, slot-based priority interrupt
> >>> schemes, and the like.
>
> >> Actually, I had already made a provision for this possibility.  The
> >> XBUS (on the bottom of the board), and the YBUS (between the two plane
> >> layers) are routed between the J7-J20 pins on their respective layers.
> >>   The actual short traces (0.200" long) from the J7-J20 headers to the
> >> slot connectors (J1-J6) are all horizontally on the bottom layer of
> >> the board so you have full access to both the X and Y lines.
>
> > I have posted a pdf of the bottom layer (layer 4 XBUS) here:
>
> QSL
>
> I would still like the default configuration to be with a couple of
> traces daisy-chained rather than requiring surgery on ATLAS.  If surgery
> is required, fewer designs will take advantage of the feature, and there
> is a greater chance that various designers will select different pins,
> causing several wire-wrap jumpers along with multiple cuts.  If the
> daisy chain is defaulted, it can be defeated if needed by jumpers and no
> cuts.

Got it...

How about if I daisy chained the current (6) XD0-XD2 and YH0-YH2 bus
wires?  Would that give enough daisy chained connections?

73 de Phil N8VB

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