[hpsdr] [ATLAS] - proposed physical bus/pcb design 03March2006

[Lyle Johnson]

> How about if I daisy chained the current (6) XD0-XD2 and YH0-YH2 bus
> wires?  Would that give enough daisy chained connections?

Probably.  That would be one daisy chained line for a 64-pin connector, 
and three for a 96-pin.  We only need one daisy chain for a JTAG bus, 
and I suggest in the documentation we declare that XD0 be used as TDI 
and XD1 as TDO for such chaining.

I sure hope it is possible to mix vendors (e.g., Xilinx and Altera) on 
the same JTAG chain for programming purposes :-/

73,

Lyle KK7P


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