[hpsdr] ATLAS Stackup and Power decoupling

[Philip Covington]

On 3/7/06, Ray Anderson <ray.anderson at xilinx.com> wrote:
>
>
>
> The current plan of record for the ATLAS PCB stackup is:
>
>
>
> Ground Plane ----------------    Layer 1
>
> YBUS            -----------------   Layer 2
>
> Power Planes ----------------    Layer 3
>
> XBUS            -----------------    Layer 4
>
>
>
> Looking over the layout and schematic I don't see that any provisions have
> been made for discrete bypass capacitors. The only coupling between the
> Power and Ground planes is by way of the inter-plane capacitance (which is
> pretty low due to the rather thick stackup. (by the way I don't see a
> thickness spec on the ATLAS documentation, but I would assume we probably
> want to go with a standard .062 for mechanical rigidity reasons)
>
>
>
> Without some half decent bypassing (even though the data rates will be
> relatively low and the power consumption low as well) depending on the
> pwr/gnd coupling to establish a return path for the XBUS signals may open
> the design up to some unwanted simultaneous switching noise problems and
> other noise issues. The YBUS signal should be happy, but the XBUS signals
> will be clean on one edge and degraded on the other.
>
>
>
> I'd suggest at least  some token low frequency bypassing somewhere near the
> power connector (electrolytic or tantalum) and then some smaller ceramic
> decaps distributed along the board edges between the connectors to deal with
> the higher frequencies.
>
>
>
> Granted, the application boards will have local decoupling near the active
> parts (FPGAs, A/Ds and processors) but once the i/o signals and clocks get
> on the backplane making them depend on displacement current to transit
> layers to complete their return paths can be dangerous. The return image
> currents for the XBUS signal will flow back on the Power planes until  they
> reach the driver at which point, depending on whether it is a rising or
> falling edge it may need to jump  over to the Ground plane to close the
> current loop,
> 73  de Ray  WB6TPU

Hi Ray,

I will add some bypass caps to the board.

There is a new release of Kicad today that appears to fix the bug in
PCBNEW.  I will try to get the design migrated to Kicad soon.

73 de Phil N8VB

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