[hpsdr] Lionheart (updated schematic)

Christopher T. Day CTDay at lbl.gov
Sat Mar 18 10:28:54 PST 2006


Leon,

A couple of other things I don't understand and maybe you can explain:

1) I take it that you've designed this to use the full 16-bit FIFO data
path through the FX2, i.e., you've hooked up both "PortD" and "PortB" to
the FPGA. Is that right?

2) You are intending "PortA" to provide FPGA configuration info to the
EPCS chip since "PortA" is connected to the dedicated configuration FPGA
pins. Is that right?

3) On the other hand, haven't you so far been using the FX2 in Slave
FIFO mode? In that case, aren't the "PortA" pins required as input to
determine which Endpoint FIFO data is destined for or if the packet is
finished? I don't see how that addressing information gets into the FX2.
If the FX2 ran in GPIF Master mode, then the setup might work. Is that
what you had in mind? Wouldn't it be nice to leave the mode options
open?

Thanks. I'm probably just missing something obvious.


	Chris - AE6VK


-----Original Message-----
From: Leon Heller [mailto:leon.heller at bulldoghome.com] 
Sent: Saturday, March 18, 2006 9:00 AM
To: High Performance Software Defined Radio Discussion List
Subject: [hpsdr] Lionheart (updated schematic)

***** High Performance Software Defined Radio Discussion List *****

I've just corrected a couple of errors on the Lionheart schematic:

http://www.leonheller.com/lionheart/lionheart_sch.pdf

I've also uploaded the netlist, to help with the checking:

http://www.leonheller.com/lionheart/Lionheart%20(Net%20List).txt

The ground and power connections on the FPGA are implicit in the part 
definition, so I haven't bothered to connect them explicitly. They are 
connected in the netlist, of course (or should be).

73, Leon
--
Leon Heller, G1HSM
leon.heller at bulldoghome.com
http://www.geocities.com/leon_heller 

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