[hpsdr] Lionheart (updated schematic)

[Leon Heller]

----- Original Message ----- 
From: "Christopher T. Day" <CTDay at lbl.gov>
To: "Leon Heller" <leon.heller at bulldoghome.com>; "High Performance Software 
Defined Radio Discussion List" <hpsdr at hpsdr.org>
Sent: Saturday, March 18, 2006 6:28 PM
Subject: RE: [hpsdr] Lionheart (updated schematic)


Leon,

A couple of other things I don't understand and maybe you can explain:

1) I take it that you've designed this to use the full 16-bit FIFO data
path through the FX2, i.e., you've hooked up both "PortD" and "PortB" to
the FPGA. Is that right?

I think that was suggested.


2) You are intending "PortA" to provide FPGA configuration info to the
EPCS chip since "PortA" is connected to the dedicated configuration FPGA
pins. Is that right?

Yes, that's right.

3) On the other hand, haven't you so far been using the FX2 in Slave
FIFO mode? In that case, aren't the "PortA" pins required as input to
determine which Endpoint FIFO data is destined for or if the packet is
finished? I don't see how that addressing information gets into the FX2.
If the FX2 ran in GPIF Master mode, then the setup might work. Is that
what you had in mind? Wouldn't it be nice to leave the mode options
open?

Thanks. I'm probably just missing something obvious.


I'm not sure about that. Perhaps someone else can comment.

Leon 


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