[hpsdr] Lionheart (updated schematic)

[Eric Blossom]

On Sat, Mar 18, 2006 at 10:28:54AM -0800, Christopher T. Day wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> Leon,
> 
> A couple of other things I don't understand and maybe you can explain:
> 
> 1) I take it that you've designed this to use the full 16-bit FIFO data
> path through the FX2, i.e., you've hooked up both "PortD" and "PortB" to
> the FPGA. Is that right?
> 
> 2) You are intending "PortA" to provide FPGA configuration info to the
> EPCS chip since "PortA" is connected to the dedicated configuration FPGA
> pins. Is that right?
> 
> 3) On the other hand, haven't you so far been using the FX2 in Slave
> FIFO mode? In that case, aren't the "PortA" pins required as input to
> determine which Endpoint FIFO data is destined for or if the packet is
> finished? I don't see how that addressing information gets into the FX2.
> If the FX2 ran in GPIF Master mode, then the setup might work. Is that
> what you had in mind? Wouldn't it be nice to leave the mode options
> open?
> 
> Thanks. I'm probably just missing something obvious.
> 
> 	Chris - AE6VK

I also noticed that you don't have the RDY or CTL lines connected to
the FPGA.  Unless you're running short on FPGA pins, I'd connect just
about everything to the FPGA.  Also, any particular reason you're not
going for the 100 pin package?  The extra ports could be handy.

I strongly suggest hanging a 24LC025 EEPROM off of the I2C bus so
that the FX2 has it's own VID/PID/DID.  Costs $0.40 qty 1.  You can
program it in-system via the FX2, so it's really no problem at all.

Eric K7GNU

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