[hpsdr] Lionheart (updated schematic)

[Christopher T. Day]

Leon,

The more I look at this, the more I become convinced that using "PortA"
to program the EPCS _and_ using Slave FIFO mode will not work with the
56 pin version. (The Xylo doesn't work this way as "PortA" is not
connected to anything; the USRP uses "PortC" which only exists on the
100 pin and 128 pin versions, and limits what can be done with GPIF
mode.) That means the EPCS on Lionheart as designed right now can only
be programmed through the JTAG interface and not through the USB, at
least for the first time, and will not support Slave FIFO mode either. I
think we should rethink this and go with the 100 pin version at least.
I'm working on a boot note which I hope to send out soon.


	Chris - AE6VK


>> 2) You are intending "PortA" to provide FPGA configuration info to
the
>> EPCS chip since "PortA" is connected to the dedicated configuration
FPGA
>> pins. Is that right?
>>
>> 3) On the other hand, haven't you so far been using the FX2 in Slave
>> FIFO mode? In that case, aren't the "PortA" pins required as input to
>> determine which Endpoint FIFO data is destined for or if the packet
is
>> finished? I don't see how that addressing information gets into the
FX2.
>> If the FX2 ran in GPIF Master mode, then the setup might work. Is
that
>> what you had in mind? Wouldn't it be nice to leave the mode options
>> open?
>>
>> Thanks. I'm probably just missing something obvious.
>>
>> Chris - AE6VK

This is an interim board, remember. The final version will have a lot
more 
functionality.

We decided to stick with the 56 pin device, we don't really need the 
additional pins.

This is the block diagram that was agreed some weeks ago, for the final 
version:

http://www.leonheller.com/lionheart/lionheart.vsd

I basically took that, and left stuff off for this version.

Leon 



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