[hpsdr] Lionheart (updated schematic)

[Christopher T. Day]

Ok, that statement is patently wrong, so let me try again.

What I think I mean is that, on the Xylo the PortA pins of the 56 pin
FX2 are connected to non-dedicated I/O pins of the FPGA, i.e., pins
assignable by the configuration code loaded into the FPGA, and that the
pins are used while the FX2 is in Slave FIFO mode. But, PortA does _not_
appear to be connected to the dedicated FPGA configuration pins, in the
neighborhood of pins 6 to 16. If I'm counting pins the right way round,
these appear to mostly have no connection on the top of the board and
are presumably connected to the EPCS chip on the bottom of the board. I
think it was stated earlier on this reflector that the Xylo designer
confirms that it is a two layer board, so there's no other way to get
the configuration pins from the FPGA to the FX2. Hence, the FX2 doesn't
seem able to program the EPCS directly. [Didn't somebody reprogram the
"boot-PROM", i.e., the EPCS chip and discover that they couldn't do it
again through USB without reloading the "boot-PROM" through JTAG?]


	Chris - AE6VK


-----Original Message-----
From: Christopher T. Day 
Sent: Saturday, March 18, 2006 1:33 PM
To: Leon Heller; Eric Blossom
Cc: High Performance Software Defined Radio Discussion List
Subject: Re: [hpsdr] Lionheart (updated schematic)

***** High Performance Software Defined Radio Discussion List *****

> ... (The Xylo doesn't work this way as "PortA" is not
connected to anything; the USRP uses "PortC" which only exists on the
100 pin and 128 pin versions ...



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