[hpsdr] Lionheart board

Christopher T. Day CTDay at lbl.gov
Sun Mar 19 08:02:54 PST 2006


Phil,

I just glanced briefly thought Chapter 10 of the Cyclone II Device
Handbook. Yes, it is at least possible to receive (<805 Mbps) and send
(<640Mbps) LVDS signals directly on the FPGA if the right conditions are
met. One of those conditions seems to be:

The Vccio for the I/O bank containing the LVDS I/O must be 2.5V => all
the other I/O pins in that bank must use the same Vccio although they
can use different I/O protocols. From the Handbook - "an I/O bank with a
2.5-V Vccio setting can support 2.5-V LVTTL inputs and outputs, 2.5-V
LVDS-compatible inputs and outputs and 3.3-V LVCMOS inputs only."

Note that the chip in question has four I/O banks, one on each edge.
There are also placement rules for LVDS pins assignments relative to
other I/O pins; the Quartus II software will check some, but not all of
these rules.

Qustions:

1) Has anybody consciously thought about I/O protocols to be used by the
Cyclone?

2) Is this Vccio requirement too restrictive for us wrt the other I/O
pins in that bank?

3) What Vccio's do we want on the various banks?

4) What's the 1.2V regulator that is attached to the FPGA for?


Comments from knowledgeable people requested. Setting the Vccio for 1/4
of the I/O pins to 2.5V may be too restrictive if everything else we
talk to is 3.3V, in which case I guess the receiver chip goes back in.
In any event, shouldn't there be a 100ohm termination resistor on the
LDVS lines?


	Chris - AE6VK


-----Original Message-----
From: Phil Harman [mailto:pvharman at arach.net.au] 

...

1. Removed DS90LV018 that buffered LVDS input from 200MHz clock since it
is 
assumed that the FPGA can take LVDS inputs directly - please confirm.

...

Feedback requested please.

73's Phil...VK6APH 



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