[hpsdr] Lionheart board

[Lyle Johnson]

> Qustions:
> 
> 1) Has anybody consciously thought about I/O protocols to be used by the
> Cyclone?
> 
> 2) Is this Vccio requirement too restrictive for us wrt the other I/O
> pins in that bank?
> 
> 3) What Vccio's do we want on the various banks?

I suggest considering running all the IO at 3.3V and leave the LVDS 
input buffer in place.  If someone makes a mistake and applies the wrong 
voltage to the LVDS inputs, the buffer is much cheaper and easier to 
replace than the FPGA.

> 4) What's the 1.2V regulator that is attached to the FPGA for?

The core (logic) supply for the FPGA.

73,

Lyle KK7P


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