[hpsdr] Lionheart to Atlas bus signals...

[Christopher T. Day]

Leon,

There is an I2C Master on OpenCores:

<
http://www.opencores.org/projects.cgi/web/i2c/overview
>

I started looking at this but distracted myself with Wishbone example
code. I looked somewhat at the Verilog I2C Master code in the
rtl/verilog subdirectory. For testing, there are both an I2C Slave Model
and an SPI Slave Model in bench/verilog. The I2C Slave Model looks
pretty thorough; maybe one can "just" replace the debug messages with
whatever you want the Slave to do. [Sentences with "just" in them are
nearly always wrong.] I haven't actually tested them yet.

There are also a couple of I2C Slave implementations on the Xylo pages:

<
http://www.fpga4fun.com/I2Cslave1.html
>
<
http://www.fpga4fun.com/files/I2Cslave1.zip
>
<
http://www.fpga4fun.com/ExternalContributions/VHDL_i2cs_rx_CPLD.zip
>

Haven't tried these either, but the problems they talk about seem to be
related to getting a clean SCL signal from the outside world. The
following link might help.

<
http://www.xilinx.com/xcell/xl19/xl19-34.pdf
>



Chris - AE6VK


-----Original Message-----
From: Leon Heller [mailto:leon.heller at bulldoghome.com] 
...

There might be a problem with I2C on the FPGA, has anyone actually 
implemented it? SPI is quite easy, on the other hand.

Leon 

---


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