[hpsdr] Fw: Lionheart to Atlas bus signals...

[Leon Heller]

----- Original Message ----- 
From: "Phil Harman" <pvharman at arach.net.au>
To: "High Performance Software Defined Radio Discussion List"
<hpsdr at hpsdr.org>
Sent: Monday, March 20, 2006 1:30 PM
Subject: [hpsdr] Fw: Lionheart to Atlas bus signals...


> ***** High Performance Software Defined Radio Discussion List *****
>
> Hi All
>>>
>>> Leon,
>>>
>>> There is an I2C Master on OpenCores:
>>>
>>> <
>>> http://www.opencores.org/projects.cgi/web/i2c/overview
>>>>
>>>
>>
> I had a look at this some time ago. The documentation is very good and it
> is
> a comprehensive implementation of an I2C master. It's really intended for
> the opencores.org  Wishbone bus but does not look too difficult to use on
> its own.
>
> I've made a change to the Lionheart block diagram to show the FPGA sitting
> in the I2C bus rather than passing it through. That way we can have either
> the FPGA or the FX2 as the I2C master. There was already an 24LC64 sitting
> on the I2C that was intended to be used by the  FX2.  I've also brought
> the
> I2C bus out to the edge of the PCB for future use.  Lyle, what protection
> would you suggest we put on the I2C at the board edge?
>
> I allowed for an MCP120T Power On Reset chip - does the FPGA have a
> dedicated reset pin or can we assign any I/O pin  to this function?

The FPGA doesn't actually have a reset capability as such. It powers up
without any configuration and has to be configured externally, via the
EPCS1, JTAG or FX2, in our case. Individual functions inside the FPGA may
have their own reset, via an I/O pin.

Leon


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