[hpsdr] [OZY] No BGA for OZY

[Philip Covington]

Hi group,

I decided to stay with the EP2C5 QFP208 part for the OZY board.  The
BGA256 part adds only 16 IO pins which isn't enough to justify the
change.  I am trying to avoid the EP2C8 part because I would like to
stick with using the EPCS1 configuration device which is OK for the
EP2C5, but not the EP2C8.  The cost of the serial configuration
devices jumps considerably when you go above the EPCS1.

The current design has these changes:

1. Three RS-232 serial ports.  Two originate from the FX2 and one from
the FPGA.  As per Lyle's suggestion I have used a MAX1406 level
converter to allow true RS-232 signals.  The third RS-232 port from
the FPGA was added per Bill T.'s suggestion.  Right now all RS-232
lines share a common 2X5 header.  I am open to suggestions for
connectors/pinouts.  If you have a suggestion, please give me the
exact pinout desired but please take board space into consideration.

2. One 16 bit Logic Analyzer/Debug port.  The first eight IO lines
have optional LEDs for status/debugging purposes.  The port pinout was
done per Lyle's request for an HP/Agilent standard 2X10 pinout.

3. One 16 bit Optional Logic Analyzer/Debug port.  This port steals
some of the Cypress FX2 connections to the FPGA.  Jumpers are provided
to enable/disable this optional port.  The pinout for this port is the
same 2X10 as above.

4. Common mode choke and protection diodes added to the USB lines per
Ahti's and Phil H's suggestion.

5. I2C routed to ATLAS bus and I2C 2 pin header added per Phil H's request.

6. ATLAS_nRESET line routed to X17C1 (A19) per Lyle.

What I did not add:

A. SRAM - I figure that if we find we absolutely must have some
external SRAM for a particular application we can come up with a
plug-in daughterboard with the SRAM on it.  This would plug in to the
two 2X10 headers provided for the Logic Analyzer/Debug ports.  If we
do this we will need to supply 3.3V on one of those connectors.  I
will probably add a jumper that allows 3.3V to be supplied to pin 1 of
those 2X10 headers for this purpose.  Applications that require a lot
more SRAM than 128Kx8 should be designed as a ATLAS plug-in board.

B. Buffered inputs and outputs.  This means that protected/buffered IO
(open collector, relays, encoders, external I2C, etc...) will be done
by a separate IO board that plugs into the ATLAS bus.  An alternate
would be to make a daughterboard as in A above that allows you to use
the two 2X10 headers for this purpose.

C. Buffered I2C.  See B above.  I think that we would not need to
buffer the I2C output of the FX2 for the I2C bus lines of the ATLAS.

I can be persuaded to change my mind about the above with a strong
enough argument... ;-)

73 de Phil N8VB