[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[Philip Covington]

Hi Lyle, Ahti,

Thanks for the recommendations.  I will add those items/changes to the
schematic.  I'll wait until tomorrow though to allow others to comment
on the current state of the design.

Lyle:

I will go with the SN75C1406 and the MPC130 @ 2.7V (has internal 5 k
pullup - is that ok?).  Will determine what to do about a RS-232
connector when I get further on the pcb layout...  Any suggestions on
what ATLAS bus line to use for RESET?

Ahti:

I have already set up routing constraints/rules for the D+/D- pair in
the layout program per the Cypress TRM recommendations.  Any
suggestions on a particular USB connector (integrated magnetics or
no?).


73 de Phil N8VB

On 5/10/06, Ahti Aintila <oh2rz.sdr at gmail.com> wrote:
> Phil,
>
> The small inductor L1 from P1/pin4 to ground is useful for limiting
> the ground loop currents, but C13 should be connected to P1/pin1
> (+5V). C14 is unnecessary. Data lines from P1/pin2, pin3 to DMINUS and
> DPLUS should have a small common mode choke and overvoltage clamps
> like SN75240PW. Keep the PCB trace capacitance of the data lines small
> and well balanced.
>
> 73, Ahti OH2RZ
>
>
> On 10/05/06, Lyle Johnson <kk7p at wavecable.com> wrote:
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > Hello Phil!
> >
> > > Please review and make comments.
> > >
> > > Some initial questions:
> > >
> > > 1.  Do we need external SRAM?  There are 26 RAM blocks of 4608 bits
> > > (including parity) each in the Cyclone II EP2C5Q208C8 part that I am
> > > using.  I can probably fit in a 128Kx8 (1Mb) SRAM but, if populated,
> > > it will use up the 32 expansion IO lines that are left from the FPGA.
> >
> > I think no.  The FX2 is there primarily to act as a USB interface.
> > Extra memory might be good for buffering, but then the host computer
> > probably has lots of memory for that purpose.
> >
> > If we need a CPU in the HPSDR box with a lot of memory, we may want to
> > just make a board that provides that, along with the IO we might want
> > for local control, CAN bus, etc.  Perhaps an ARM or something similar.
> >
> > > 2. Are 8 optional SMT LEDs tied to the FPGA_GPIO[1-8] lines enough for
> > > status/debugging use?  These would not be of much use if I add the
> > > SRAM to those lines, so that is why I call them optional.
> >
> > Should be enough.
> >
> > ***
> >
> > I note that the async port lines come to a 4-pin header.  If there s
> > room, I'd like to see these buffered to RS232 levels even if we can't
> > fit a DE9 connector or pair of DE9 connectors to the board.  Almost
> > anyone who uses these lines is going to have to buffer them, so we might
> > as well do it.  We won't have charge pump noise since we have +/-12
> > available.  An SN75C1406 is small, has enough lines,and is cheap.  If we
> > lack space for a DE9, we could put in a 2x5 header that, with a
> > pin-for-pin ribbon cable would result in the correct pin out for a DE9.
> >
> > Also, I wonder if the reset line should go to an ATLAS pin?  If we have
> > several processor eventually installed, it might be good if they can
> > come out of reset at roughly the same moment so we don;t have to write
> > all sorts of code to get things sync'ed up.  A reset voltage monitor
> > chip could eliminate threshold ambiguity, such as an MCP120 series part
> > from Microchip.
> >
> > Finally, is it worth adding a physical reset button so we can bump it
> > and wonder why the FX2 rebooted?
> >
> > 73,
> >
> > Lyle KK7P
> >
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>

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