[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[Lyle Johnson]

> Anyone have any objection to going with the slower 70 ns SRAM?  If we
> used the 512Kx8 I need to come up with some extra IO pins somewhere...

128Kx8 should be plenty :-)  Could wire the location to accept either 
part, grounding or tying high the 2 extra address lines, as appropriate 
for compatibility with the 128Kx8 part.  That way we can build the board 
regardless of which part is available at the moment.

At 70 nsec plus another 30 nsec overhead delay in the FPGA, gives a 100 
nsec cycle time, and yields 80 megabit/sec bandwidth.  Since this isn't 
a FIFO, we have to cut this in half so we're down to 40 megabit/second 
"throughput".

DK has lots of x16 organized SRAM, but it is all fast/high power.  If we 
need the bandwidth...

73,

Lyle KK7P


 1147359771.0