[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[KD5NWA]

I have a Xilinx board with 1 Megabyte of 10 ns RAM that is 36 bits 
wide. That is barely enough to do a 1024x768 by 512 color display. 
You have to plan ahead for future possibilities.

Think in color, and you won't be a dull grey.

At 10:02 AM 5/11/2006, you wrote:
>***** High Performance Software Defined Radio Discussion List *****
>
> > Anyone have any objection to going with the slower 70 ns SRAM?  If we
> > used the 512Kx8 I need to come up with some extra IO pins somewhere...
>
>128Kx8 should be plenty :-)  Could wire the location to accept either
>part, grounding or tying high the 2 extra address lines, as appropriate
>for compatibility with the 128Kx8 part.  That way we can build the board
>regardless of which part is available at the moment.
>
>At 70 nsec plus another 30 nsec overhead delay in the FPGA, gives a 100
>nsec cycle time, and yields 80 megabit/sec bandwidth.  Since this isn't
>a FIFO, we have to cut this in half so we're down to 40 megabit/second
>"throughput".
>
>DK has lots of x16 organized SRAM, but it is all fast/high power.  If we
>need the bandwidth...
>
>73,
>
>Lyle KK7P
>
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Cecil Bayona
KD5NWA
www.qrpradio.com

"Windows, the most successful software virus ever" Don Seglio Batuna 



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