[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[Alex]

> It looks like the Ozy FPGA  has about 120k bits of RAM so in theory we're OK 
> for 2 Janus boards going thru the Ozy.

What about a JANUS-like board in transmit mode, a JANUS-like board in receive mode and MERCURY in wideband receive mode? Will that work?

Looking at the USRP schematics I don't see any external RAM. 

> I am already scarce on I/O pins if we add the SRAM with the EP2C5
> QFP208 part... I guess I could bump up to the EP2C5 256 BGA part which
> would give us more I/O.  Who wants to deal with BGA's ?  No hand
> soldering there... maybe hot plate or toaster oven with paste...

If it's worth getting the extra I/O pins for the external memory, we can surmount the BGA problem
Would also make pins available for the rs-232 debugging port.

Alex, N3NP

----- Original Message ----
From: Bill Tracey <bill at ewjt.com>
To: Lyle Johnson <kk7p at wavecable.com>; Philip Covington <p.covington at gmail.com>
Cc: HPSDR List <hpsdr at hpsdr.org>
Sent: Thursday, May 11, 2006 1:57:47 AM
Subject: Re: [hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

***** High Performance Software Defined Radio Discussion List *****

Man, I've got to get a wide format printer ... reading these things on 8 
1/2 x 11 is for the birds!

One thing Phil H has done debugging the Xylo is to have an RS 232 out that 
he can write to from within the FPGA for debugging.  I'd planned to add one 
of the FTDI serial -> USB chips to my Xylo to be able to do this via a USB 
port.  Any interest in doing this on the Ozy's FPGA?  If so I can try and 
get the FTDI setup prototyped on the Xylo over the weekend -- I prefer the 
FTDI USB Serial to a conventional RS232 port because RS2 ports are becoming 
scare and in either case you need to add a chip - either a Serial USB 
converter, or a level converter.

As to external RAM ... on the Xylo with the current FPGA code we're using 
40k out of the 60k bits in the FPGA.  Most of the bits are used for FIFOs 
between the A/D and D/A converters and the FX2 USB transmit/receive 
FIFOs  (4kbytes on the PC->FPGA side, 1kbytes on the FPGA->PC side).    It 
looks like the Ozy FPGA  has about 120k bits of RAM so in theory we're OK 
for 2 Janus boards going thru the Ozy.

Since we'll be able to to do the setup and config of the FX2 USB FIFOs  we 
may not need as much FIFO space on an Ozy solution.  Also as long as we 
stick with sampling data rates that are integral multiples of each other 
(ie 1 frame sent per frame received,  1 frame sent per 2 frames received 
etc)  we may not need as much FIFO space -- the case we ran into the need 
for large FIFO space was when we needed to send on non integral multiples 
of the receive frame rate

Given the uncertainty in how much FIFO space we will need to maintain 
glitch free audio, I'm a bit nervous on how scarce the RAM bits may 
become.  so keeping some capability for an external RAM at this point seems 
to be a good idea.   If we never populate it great, the 32 pins can be used 
for other things.

Another thing to look at to see if we will need the external RAM is the 
USRP -- does it have any?  Anyone know how much of the FPGA RAM the USRP is 
using?   I have one - will try and look into to it over the weekend.

Regards,

Bill

At 03:19 PM 5/10/2006, Lyle Johnson wrote:
>***** High Performance Software Defined Radio Discussion List *****
>
>Hello Phil!
>
> > Please review and make comments.
> >
> > Some initial questions:
> >
> > 1.  Do we need external SRAM?  There are 26 RAM blocks of 4608 bits
> > (including parity) each in the Cyclone II EP2C5Q208C8 part that I am
> > using.  I can probably fit in a 128Kx8 (1Mb) SRAM but, if populated,
> > it will use up the 32 expansion IO lines that are left from the FPGA.
>
>I think no.  The FX2 is there primarily to act as a USB interface.
>Extra memory might be good for buffering, but then the host computer
>probably has lots of memory for that purpose.
>
>If we need a CPU in the HPSDR box with a lot of memory, we may want to
>just make a board that provides that, along with the IO we might want
>for local control, CAN bus, etc.  Perhaps an ARM or something similar.
>
> > 2. Are 8 optional SMT LEDs tied to the FPGA_GPIO[1-8] lines enough for
> > status/debugging use?  These would not be of much use if I add the
> > SRAM to those lines, so that is why I call them optional.
>
>Should be enough.
>
>***
>
>I note that the async port lines come to a 4-pin header.  If there s
>room, I'd like to see these buffered to RS232 levels even if we can't
>fit a DE9 connector or pair of DE9 connectors to the board.  Almost
>anyone who uses these lines is going to have to buffer them, so we might
>as well do it.  We won't have charge pump noise since we have +/-12
>available.  An SN75C1406 is small, has enough lines,and is cheap.  If we
>lack space for a DE9, we could put in a 2x5 header that, with a
>pin-for-pin ribbon cable would result in the correct pin out for a DE9.
>
>Also, I wonder if the reset line should go to an ATLAS pin?  If we have
>several processor eventually installed, it might be good if they can
>come out of reset at roughly the same moment so we don;t have to write
>all sorts of code to get things sync'ed up.  A reset voltage monitor
>chip could eliminate threshold ambiguity, such as an MCP120 series part
>from Microchip.
>
>Finally, is it worth adding a physical reset button so we can bump it
>and wonder why the FX2 rebooted?
>
>73,
>
>Lyle KK7P


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