[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[Lyle Johnson]

>> It looks like the Ozy FPGA  has about 120k bits of RAM so in theory we're OK 
>> for 2 Janus boards going thru the Ozy.
> 
> What about a JANUS-like board in transmit mode, a JANUS-like board in receive mode and MERCURY in wideband receive mode? Will that work?

You can put in two JANUS.  You can put in more than two, in fact.  I 
suspect you could put in more than 1 Mercury as well. In fact, you could 
put in more than 1 Ozy if you need more USB bandwidth, or had horribly 
asymmteric/irrational sample rate relationships to deal with and let the 
PC do the buffering....

> Looking at the USRP schematics I don't see any external RAM. 
> 
>> I am already scarce on I/O pins if we add the SRAM with the EP2C5
>> QFP208 part... I guess I could bump up to the EP2C5 256 BGA part which
>> would give us more I/O.  Who wants to deal with BGA's ?  No hand
>> soldering there... maybe hot plate or toaster oven with paste...
> 
> If it's worth getting the extra I/O pins for the external memory, we can surmount the BGA problem
> Would also make pins available for the rs-232 debugging port.

I'd like to avoid BGA if at *all* possible.  You can melt solder on a 
hot plate or toaster oven, and if you are skilled you might even get it 
right, but this stuff is extremely difficult to inspect and with 
production runs measured in 1s to 10s of units, it is going to be pretty 
tough to get it right.

I'd toss out the third RS232 port *and* the external RAM before I'd 
consider BGA.

Remember, Ozy's main function is to provide a USB interface between the 
HPSDR and the attached PC.

Just my opinion.

73,

Lyle KK7P


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