[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments - May 10, 2006

[Eric Blossom]

On Thu, May 11, 2006 at 07:39:10AM -0700, Alex wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> > It looks like the Ozy FPGA  has about 120k bits of RAM so in theory we're OK 
> > for 2 Janus boards going thru the Ozy.
> 
> What about a JANUS-like board in transmit mode, a JANUS-like board
> in receive mode and MERCURY in wideband receive mode? Will that
> work?
> 
> Looking at the USRP schematics I don't see any external RAM. 

You're right.  It doesn't have any.  We build the FIFO's that we use
to buffer between the FX2 and the FPGA out of FPGA ram.  We allocate
enough to buffer a few USB packets in each direction.  We're also
running the FX2 quad buffered, so there's a reasonable amount of
buffering in the system.  On the EP1C12, we're using about 50% of the
RAM.  We probably don't need to use that much for fifos, but we
weren't using it for anything else...

Eric

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