[hpsdr] [OZY] Initial OZY Schematic Posted For Review and Comments- May 10, 2006

[Christopher T. Day]

Phil,

I yield on the SRAM for the FX2 question. As long as the I2C EEPROM is
there, I'll get by. And with the intrinsic RAM of the FPGA, I doubt that
anything more is needed on that side either.


	Chris - AE6VK


P.S. - I'm about to order an I2C EEPROM for my Xylo so I can play around
with boot processes and things. I want to see if I can get Cypress'
"Streaming Over USB" Reference Design going on the Xylo.


-----Original Message-----
From: Philip Covington [mailto:p.covington at gmail.com] 
Sent: Wednesday, May 10, 2006 12:54 PM
To: HPSDR List
Subject: [hpsdr] [OZY] Initial OZY Schematic Posted For Review and
Comments- May 10, 2006

***** High Performance Software Defined Radio Discussion List *****

Hi group,

In SVN and here:

<http://www.hamsdr.com/personaldirectory.aspx?id=231>

I have posted the initial schematic for the OZY board design.  It is
in PDF format.

Please review and make comments.

Some initial questions:

1.  Do we need external SRAM?  There are 26 RAM blocks of 4608 bits
(including parity) each in the Cyclone II EP2C5Q208C8 part that I am
using.  I can probably fit in a 128Kx8 (1Mb) SRAM but, if populated,
it will use up the 32 expansion IO lines that are left from the FPGA.

2. Are 8 optional SMT LEDs tied to the FPGA_GPIO[1-8] lines enough for
status/debugging use?  These would not be of much use if I add the
SRAM to those lines, so that is why I call them optional.

73 de Phil N8VB
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