[hpsdr] [OZY] Schematic Update for 11 May 2006

[Lyle Johnson]

Hello Phil!

> Here is the updated OZY schematic in PDF format for 11 May 2006:
Couple of minor suggestions (minor to make, maybe less minor to 
implement :-)


SHEET 1)

D14 and D16 should be tied to +3V3 or +5 rather than +12, I think.

SHEET 2)

Consider making the configuration mode select jumpers through hole 1x3 
male headers,  That way it is easy to reconfigure during development, 
and obvious what the present selection is.

SHEET 3)

If you decide to feed power to pin 1 of the debug ports to support a 
piggyback SRAM, consider using a Shottky diode (BAT54 or similar in 
SOT23).  That way, if the logic analyzers connected, its +5V won't do 
any damage, and it wont; be loaded by the +3V3 line.


If a pin-for-pin IDC to DE9 cable is fabricated, the pins will map thus:

HDR DE9
  1 - 1
  2 - 6
  3 - 2
  4 - 7
  5 - 3
  6 - 8
  7 - 4
  8 - 9
  9 - 5
10 - n/a

If a DE9S is attached, I think the following signal configuration would 
map async port 0 to the connector which could then drive a 3-wire serial 
port connection, and the directions of the other signals would be 
consistent so there would be no conflicts if a full port were attached.

HDR    SIGNAL   RS232
  1 -  +5 ?      (DCD)
  2 - RS232_TXD1 (DSR)
  3 - RS232_TXD0 (RXD)
  4 - RS232_RXD2 (RTS)
  5 - RS232_RXD0 (TXD)
  6 - RS232_TXD2 (CTS)
  7 - RS232_RXD1 (DTR)
  8 - +5 ?       (RI )
  9 - GND        (GND)
10 -

73,

Lyle KK7P


 1147388766.0