[hpsdr] JTAG explanation and sample code

[Gerda & Kevin]

Thanks for the pointer Phil, I too found this information most informative,
& does clear up some of my uncertainties.

Can I assume we will be using the JTAG chain for programming the multiple
FPGA’s?

If so what will be the PC software requirements,
Xilinx's ISE WebPack / Altera's Quartus II Web Edition?, I guess this will
be dependant 
upon the specific FPGA’s selected? Or is there a generic JTAG software
programmer?

What JTAG cable should I be investing in ? USB / parallel? 
If parallel where can I purchase one or how do I homebrew one (preferred)?

While trying to grasp the basics, what code snippets should I be looking at,
Verilog or VHDL?

Apologies for the newbie queries but all this FPGA technology is new to me 
& I’m here for the ride, on a steep learning curve, and enjoying every
moment,
aint this a great hobby!

Kevin 
M0KHZ
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