[hpsdr] JTAG explanation and sample code

[Lyle Johnson]

> Can I assume we will be using the JTAG chain for programming the 
> multiple FPGA’s?

ATLAS is designed to support this.  The individual modules will have to 
support it, too.  So the best answer is: probably.

> If so what will be the PC software requirements,
> Xilinx's ISE WebPack / Altera's Quartus II Web Edition?, I guess this 
> will be dependant upon the specific FPGA’s selected?

Correct.

> Or is there a generic JTAG software programmer?

<www.amontec.com> for a widget than will work with Altera, Xilinx, etc. 
  Not cheap, though.

> What JTAG cable should I be investing in ? USB / parallel?

If you have a parallel port,ther parallel port devices are cheaper.

> If parallel where can I purchase one or how do I homebrew one (preferred)?

I think you'll find the details on the Altera site for the Altera 
Byteblaster.  So far, the CPLDs and FPGAs are Altera in the HPSDR 
project.  There is no guarantee that future boards will use Altera.

<http://www.digilentinc.com/> has lots of inexpensive programming 
dongles, though focused on Xilinx products.

> While trying to grasp the basics, what code snippets should I be looking at,
> Verilog or VHDL?

JTAG doesn't care.  For FPGA stuff, either is suitable.

A book you might find interesting is "HDL Chip Design" bu Douglas Smith, 
  ISBN 0-9651934-3-8.  It is copyright 1996, my copy is the 8th printing 
which contains some revisions and updates and was printed in October 
2000. I don't know if a newer edition is available.

This book covers the fundamentals of Verilog and VHDL, and gives all 
sorts of practical examples of logic using both languages for each and 
every example.

Enjoy!

73,

Lyle KK7P


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