[hpsdr] What can we do with 2 cards

kd5nwa at cox.net kd5nwa at cox.net
Sat May 13 09:53:16 PDT 2006


That was the original plan, a two board system to connect to a SDR
transceiver, but it's gotten too complicated since then, that why I
bailed out. Soon at the rate it's going, you going to need 4 to five
boards to run the radio, that will be rather an expensive solution to a
simple problem. With a two board system, you can still add other boards
for more specialized projects, but boys love they complicated toys.

Good luck.



On Sat, 2006-05-13 at 05:24 -0700, Alex wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> I'm going to bring up my question from earlier. 
> 
> 
> Why not move the parallel port DSR-1000 control onto JANUS?
> 
> 
> Then we have a 2 board solution (plus the backplane). SDR-1000 users can take advantage of other cards like:
> GIBRALTAR -  to provide the 10MHz reference signal to the SDR-1000
> SASQUATCH and the it-who-is-not-named gp I/O board  - or computerless SDR-1000 operation
> (the gp I/O board can also replace the UCB).
> 
> My vote is not to regress the OZY design, but to put the SDR-1000 interface system requirements onto JANUS.  
> I know one argument put forward was:
> Why send the SDR-1000 control commands down the ATLAS bus, deal with them at the OZY.
> 
> Well, since we're going to have to handle other i/o commands coming from the host computer and sending them to the gp I/O card, why not let JANUS deal with the i/o for the SDR-1000.
> 
> I am advocating to not assume SDR-1000 will always be "state of the art", but nor to ignore that installed user base.
> The current card interfacing structure of the SDR-1000 leaves lots to be desired, the HPSDR can provide a good platofrm for expansion.
> 
> No, I don't own any SDR-1000s
> 
> We need to keep thinking everything through so the HPSDR will meet the requirements from the two interest areas:
> 
> (a) SDR-1000 upgrading
> (b) HPSDR as a full-up SDR itself (and as a real neat and useful generic benchtop device)
> 
> Those are my 2 cents
> 
> Alex, N3NP
> 
> 
> ----- Original Message ----
> From: Philip Covington <p.covington at gmail.com>
> To: Bill Tracey <bill at ewjt.com>
> Cc: HPSDR List <hpsdr at hpsdr.org>
> Sent: Saturday, May 13, 2006 7:57:01 AM
> Subject: Re: [hpsdr] What can we do with 2 cards
> 
> ***** High Performance Software Defined Radio Discussion List *****
> 
> Hi Bill,
> 
> If we agree to forgo the Logic Analyzer/Debug Port(s) and also agree
> that we will never expect to add external SRAM then I can drop the I2C
> IO stuff and provide somewhere around 32 I/O off the OZY.  I think you
> can do all 3 below then.  Then we need to discuss how to
> protect/buffer those lines in a way to allow all 32 to be inputs,
> outputs, or a combination of both.
> 
> I am leaving soon this morning, and on the drive to/from home I will
> be thinking more about this.
> 
> 73 de Phil N8VB
> 
> 
> On 5/13/06, Bill Tracey <bill at ewjt.com> wrote:
> > ***** High Performance Software Defined Radio Discussion List *****
> >
> > When we started down this path with the Xylo I think one of the
> > configuration goals we had was:
> >
> >          1. Sound Card replacement
> >          2. Ultra Low Latency CW input
> >          3 .SDR 1000 Parallel Port Control
> >
> > As we morphed to HPSDR my hope was that this configuration could be done
> > with two cards - Audio (Janus) and USB/FPGA (Ozy)
> >
> > At the moment it looks like we may only be able to do #1 with 2 cards.  We
> > might be able to do #1 & #2 if we can get low latency CW keying via I2C I/O
> > via FX2.    We certainly cannot do #3 with just 2 cards.  At the moment on
> > the Xylo prototypes we've got PTT/DOT and DASH coming thru FPGA pins and
> > their state gets integrated into the audio data stream going to the radio,
> > giving very low latency..  Doing CW via I2C via FX2 may have sufficiently
> > low latency, not sure of this.  I'd assume we'd have to read from an FX2
> > USB endpoint to get the status of the ports -- anyone know if one can do a
> > blocking read waiting for the state of the I2C ports to change from the PC
> > -- hate the idea of having to poll the USB port at a hi rate for good CW
> > performance.       I don't think we can do SDR 1000 parallel port control
> > with the I2C expander as it takes 17 (D0-7, C0-3, S3-S7)  lines, also not
> > clear to me  how quickly we can and need to wiggle those lines to program
> > the DDS in the SDR 1000 when going via an I2C.
> >
> > One idea to get back to doing dot/dash directly thru the FPGA is to go
> > through the Janus.  It looks like there are 4 unused I/O on the Janus
> > CPLD.  Could we add some protection circuitry on the Janus to 2 of those
> > lines and configure the CPLD to put those sigs on the Atlas bus.   Maybe
> > add 3 more pins to the 0.100 unbalanced audio connector?
> >
> > I that's not  viable, is there space for protection circuitry for 2 lines
> > on the Ozy  and a 3 pin connector?  Could we jumper the configuration of
> > the FPGA serial port such that it's either tied to the level converter or
> > the external connector?
> >
> > Just some late night thoughts -- trying to find a way to get a little more
> > function into a 2 board setup.
> >
> > Regards,
> >
> > Bill (kd5tfd)
> >
> >
> >
> >
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