[hpsdr] Janus Rev B Update

[Phil Harman]

Helmut,

I must admit that I don't quite understand your concern over the PWM D/A 
converter but here are the figures you wanted.

It uses over-sampling at ~6MHz and is a standard 1 bit D/A. Since it is 
implemented in the FPGA you can really make any changes you want to it. 
Here is the Verilog:

/////////////////////////////////////////////////////////////////

//

// Single bit PWM 16 bit D/A converters

//

/////////////////////////////////////////////////////////////////

reg [15:0] I_Data;

reg [15:0] Q_Data;

reg [15:0] I_Data_in;

reg [15:0] Q_Data_in;

reg [16:0] I_PWM_accumulator;

reg [16:0] Q_PWM_accumulator;



always @(negedge BCLK)

begin

I_Data_in <= I_Data + 16'h8000; // so that 0 in gives 50:50 mark/space

Q_Data_in <= Q_Data + 16'h8000;

I_PWM_accumulator <= I_PWM_accumulator[15:0] + I_Data_in;

Q_PWM_accumulator <= Q_PWM_accumulator[15:0] + Q_Data_in;

end

assign I_PWM_out = I_PWM_accumulator[16]; // send to FPGA pins

assign Q_PWM_out = Q_PWM_accumulator[16];


As I have it set up it is 16 bits and data is updated at 48kHz. That gives a 
theoretical DR of 96dB. I've not actually measured the S/N ratio but unless 
there is a real problem with the PCB layout it's going to be way more than 
we need for the transmitter I/Q signals.

If you could please explain in more detail exactly what your concerns are 
then I'll try and address them.

73's Phil... VK6APH



----- Original Message ----- 
From: "vk4str" <vk4str at netspace.net.au>
To: "Lyle Johnson" <kk7p at wavecable.com>
Cc: <links at hpsdir.org>; <hpsdr at hpsdr.org>
Sent: Tuesday, May 16, 2006 3:32 PM
Subject: Re: [hpsdr] Janus Rev B Update


> ***** High Performance Software Defined Radio Discussion List *****
>
> Phil, Bill and Lyle,
>
> I understand that you have PWM output working on the prototypes. Could
> you please provide details of PWM data resolution and sampling rate,
> etc. I would like to determine the SNR that can be achieved with PWM. In
> other words what will the achieveable SNR and maximum BW of the PWM
> modulator be with the proposed OZY FPGA?
>
> Lyle, the Line-out on the TLV could be used for TX-IF. Then we should
> best provide an headphone/speaker amplifier after the PWM, just in case.
>
> Thanks, Helmut
>
> Lyle Johnson wrote:
>>> Nice job! However, as I have discussed before with Phil_H, this design
>>> may not be full duplex capable, ie useable to work a satellite
>>> transponder. I understand that PWM has certain limitations, please
>>> correct me if I am wrong.
>>
>>
>> I believe this is a full duplex solution.
>>
>>> The AK5394A is used for RX and the processed audio is output on the
>>> speaker or headphone of the TLV320AIC23B.
>>>
>>> The TX audio is fed to the MIC input of the TLV with the only TX
>>> output option being PWM. The Line-out cannot be used if the speaker is
>>> in use.
>>>
>>> Would a DAC for TX output not be a better option? I somehow dont trust
>>> that the PWM option will be satisfactory for TX.
>>
>>
>> A DAC could certainly be used.  I think that Phil and Bill want to play
>> with PWM for this, and if it works well for Tx IF it is a cheap and
>> linear solution.
>>
>> Note also that the PWM *could* be used for user audio "line" output and
>> the line out or phones out could then be used for Tx IF.  This would be
>> limited to 48 or 96 kHz sampling rates, of course.
>>
>> 73,
>>
>> Lyle KK7P
>>
>>
>
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