[hpsdr] Janus Rev B Update

[vk4str]

Hi Phil,

Thank you for the explanation. It seems that with your given 
specification there should not be any of the known PWM problems to be 
expected that I have read about in a number of newsgroups. These 
obviously come from insufficient oversampling or lack of processing 
power etc. The Cyclone II hopefully has more than enough power so as not 
to starve the PWM oversampling.

I will miss watching the progress of HPDSR while I am on an overseas 
trip for the next 4 weeks. Sadly I will miss out on Dayton though.

Hope to be able to catch up when I am back.

73, Helmut


Phil Harman wrote:
> Helmut,
> 
> I must admit that I don't quite understand your concern over the PWM D/A 
> converter but here are the figures you wanted.
> 
> It uses over-sampling at ~6MHz and is a standard 1 bit D/A. Since it is 
> implemented in the FPGA you can really make any changes you want to it. 

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