Re: [hpsdr] Ozy – Schematic OZY_REVXA3.sch (comments)

[Philip Covington]

Hi Kevin,

See comments in line below:

On 5/17/06, Gerda & Kevin <g5rda at tiscali.co.uk> wrote:

> Phil, this may not be significant / or an issue, however,
> I have been reviewing your latest schematic and my eyes are telling me that:
>
> Cyress USB chip nets:
>
> FX2_T1 – pin 30
> FX2_T2 – pin 31

These go to test points right now.

> FX2_PC6 – pin 78
> FX2_PC7 – pin 79 &

These are connected to the FPGA (pin 3 & pin 48)

> FX2_INT5 – pin 106 are all unused (& probably correct so).

To a test point for now...

> Cyclone II EP2C5-208 nets:
>
> FPGA_DATA0 – pin 20

To pin 7 or HDR2...

> FPGA_DCLK – pin 21 &

To pin 1 of HDR2...

> FPGA_NCEO are unused (& probably correct)

So far yes...

> I also think pin 118 (currently assigned – ATLAS_X17C1) should be assigned ATLAS_NRESET.
> That's assuming the USB reset is usually from the FPGA & not the Atlas bus.

See jumper J14.  This allows optional connection of ATLAS_NRESET to ATLAS_X17C1

There will be some significant changes tonight...in REVXA.4

73 de Phil N8VB

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