[hpsdr] Ozy – Schematic OZY_REVXA3.sch (comments)

[Gerda & Kevin]

Phil, this may not be significant / or an issue, however,
I have been reviewing your latest schematic and my eyes are telling me that:

Cyress USB chip nets:

FX2_T1 – pin 30
FX2_T2 – pin 31
FX2_PC6 – pin 78
FX2_PC7 – pin 79 &
FX2_INT5 – pin 106 are all unused (& probably correct so).

Cyclone II EP2C5-208 nets:

FPGA_DATA0 – pin 20
FPGA_DCLK – pin 21 &
FPGA_NCEO are unused (& probably correct)

I also think pin 118 (currently assigned – ATLAS_X17C1) should be assigned
ATLAS_NRESET.
That’s assuming the USB reset is usually from the FPGA & not the Atlas bus. 
Great work I really don't know how you guys can be so productive?

The provisional layout looks great!

Kevin
M0KHZ
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