[hpsdr] [OZY] Schematic Update May 18, 2006 - REVXA.5

Christopher T. Day CTDay at lbl.gov
Fri May 19 15:43:58 PDT 2006


Phil,

If I read the schematic correctly, there is no access to the JTAG chain
other than through the JTAG connector on Ozy. Since the JTAG pins are
dedicated on the Cyclone II, there's no way to get access to them from
inside the Cyclone's configuration file. What's bothering me is how the
firmware/configuration files of CPLD/FPLA's on other boards get updated.
If there were some way to access the JTAG lines from the FX2, everything
could be programmed through the USB port via JTAG, particularly CPLDs =>
no additional hardware needed for users to update their radios. Without
the connection, some form of JTAG adapter is required along with mucking
about inside the box. I get the feeling you've exhausted all the
available pins on the big IC's, but I thought I'd point out this
consequence of the design.


	Chris - AE6VK


-----Original Message-----
From: Philip Covington [mailto:p.covington at gmail.com] 
Sent: Thursday, May 18, 2006 12:09 PM
To: HPSDR List
Subject: [hpsdr] [OZY] Schematic Update May 18, 2006 - REVXA.5

***** High Performance Software Defined Radio Discussion List *****

Hi group,

Today's update to the OZY schematic (REVXA.5) has been posted to:

<http://www.philcovington.com/HPSDR/OZY/REVXA.5/>  and also HPSDR SVN.

Top and Bottom PCB Assembly prints posted in PDF format also.

Changes:

1. Changed LVDS parts DS92LV010 to SN65LVDM050D.  The DS92LV010A would
allow us to  send a ~50 - 100 MHz clock off of the board.  For two
clock inputs and two clock outputs we needed 4 parts.  The single
SN65LVDM050D replaces the 4 DS92LLV010 parts and allows > 200 MHz
clock rates.

2. Component position changes.

3. Silkscreen adjusted and now shown on Top and Bottom Assembly print.

73 de Phil N8VB
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