[hpsdr] New RF Digitizer

[Lyle Johnson]

>> The AD6636 certainly looks like a fast path to get what appears to be
>> good performance, quickly.  The FPGA of course is more flexible at the
>> cost of higher power consumption and more opportunity to learn/tweak/etc.
> 
> When things settle down here I want to go back through the various
> verilog DDC stages and see what sized Cyclone II we would have to use
> to fit them all in.  I prefer the FPGA path if we can pull it off
> without going to $200+ devices :-)

Or, if we have the space on the board and it won't compromise the skew 
integrity after the ADC output buffer -- or input noise -- , we could 
put in *both*.  This would allow us to get up and running quickly, and 
also give us a means to directly compare the FPGA implementation to the 
AD6636 implementation of the DDC.

Lyle KK7P


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