[hpsdr] Odyssey Cyclops Schematics

[Lyle Johnson]

Hello Joseph!

This is exciting news!

A couple of notes:

1) Be sure you have a positive control way to switch power on and off to 
the Odyssey system.  The XC2C384 CPLDs are in reality SRAM-based with 
local Flash to load at power up, like the EPM240 on Janus except the XC2 
parts are in reality CPLDs rather than FPGAs masquerading as CPLDs.  See 
"Power Up Characteristics" page 12 of the Cool Runner 2 Product 
Specification (Xilinx DS090 (v2.7) July, 2006.

The issue is radiation chaining the configuration and no easy way to 
tell if that happened.

For a recent launch, I had to scramble at the last minute and revise a 
design that used CoolRunner parts for this very reason.

2) The video capture inputs (RCA phono jacks) would be better along the 
right edge of the PCB rather than the top edge to be consistent with 
other HPSDR modules.

3) IF pins are available, and a CPLD or similar can be put on the Siren 
or Odeyessus boards, the "hard use" of the Atlas pins on J1A{2..3] and
J1C[2..15] can be made malleable.

Great work, Joseph! And it was a pleasure to meet you at the TAPR 25th 
Anniversary DCC last weekend.

73,

Lyle kK7P


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