[hpsdr] Verilog vs VHDL

[k5nwa]

Which is more user friendly? I'm trying to decide between Verilog and 
VHDL for a FPGA project and wanted some opinions on the subject 
before I go out and spend some money on books. The project will 
involve mostly processing of I/Q audio streams and some video display 
control, so a big issue will be math processing.

I'm leaning heavily towards Verilog since it seems less wordy than 
VHDL, and there are some in this group that are familiar with it.

Any thoughts?

Cecil
KD5NWA
www.softrockradio.org  www.qrpradio.com

"Blessed are the cracked, for they shall let in the light."