[hpsdr] Blackfin 32*32 bit multiply

[Philip Covington]

On 8/20/07, Greg Overkamp <overkamp at yahoo.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> > Hello
> > The both MAC of the Blackfin can be coupled to
> > obtain a 32*32 bits MAC
> > with 80 bits accumulator.
> > I use these devices under uClinux for a video
> > compression project.
> > Under uClinux you get all the gnu toolchain for free
> > , Analog has ported
> > an optimised lib for DSP processing .
> > By coupling both MACs you get "only" 600 MMACs per
> > second @600MHz.
> > To interface A/D or the FPGA there the PPI bus which
> > is a 16 bits
> > synchronous parallel port originally aimed for video
> > application with
> > dedicated DMA modes.
> > These processors are cheap & powerfull .
> > You also can use PPI to drive a flat panel.
> >
> > 73
> > Chris HB9TLN
> >
>
> Chris,
>
> I cannot find anywhere in the Blackfin Processor
> Programming Reference (rev 1.2 Feb 2007) any
> information regarding a single-cycle 32*32 multiply
> with 80-bit accumulate. On page 2-36 I can see the
> dual 16*16 MACs into 40-bit acc, and on page 2-46 I
> see the three-cycle 32*32 MAC into a (fairly useless)
> 32-bit accumulator.
>
> Your statements "The both MAC of the Blackfin can be
> coupled to obtain a 32*32 bits MAC with 80 bits
> accumulator" and "By coupling both MACs you get 600
> MMACs per second @600MHz" seems to imply that the
> Blackfin supports single-cycle 32*32 MACs into an
> 80-bit accumulator. I would be very interested in
> seeing the assembler instruction to accomplish this or
> the page number in the Programming Reference that
> provides more information on this single-cycle 32*32
> MAC with 80-bit result.
>
> Greg
> WD9DEX

I'll admit that  I only took a cursory look at the Blackfin
documentation, but I did not see an obvious way of doing this.  I'd
like to know too.

73 Phil

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