[hpsdr] Verilog vs VHDL

[Eric Blossom]

On Wed, Aug 29, 2007 at 03:10:22PM -0700, Lyle Johnson wrote:
> ***** High Performance Software Defined Radio Discussion List *****
> 
> > Which is more user friendly?
> 
> Depends on the user ;-)
> 
> > I'm trying to decide between Verilog and 
> > VHDL for a FPGA project and wanted some opinions on the subject 
> > before I go out and spend some money on books...
> > 
> > I'm leaning heavily towards Verilog since it seems less wordy than 
> > VHDL, and there are some in this group that are familiar with it.
> > 
> > Any thoughts?
> 
> Both camps have their adherents, and both languages are different enough 
> that it is not always easy to translate between them.
> 
> I suggest looking at some code for simple things, perhaps code for an 
> app note done both ways on the Altera and/or Xilinx websites, then decide.
> 
> Most of the work being done on the boards so far in the HPSDR project 
> are in Verilog.  I use VHDL only because I had access to a decent 
> simulator for it and not for Verilog when I took the plunge a few years 
> ago, so I've not been very active in FPGA coding here.
> 
> Enjoy!
> 
> Lyle KK7P

FWIW, "HDL Chip Design" by Douglas J. Smith has side-by-side
implementations of stuff in both Verilog and VHDL.

Eric K7GNU

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