[hpsdr] JanusCPLD_Verilog code

[Gerda & Kevin]

Thanks guys, I’m having great fun!
As a budding ‘hacker’ I’ve been playing around with Quartus II and the Janus
code on the SVN.
 
This is probably a very stupid question but, after compiling both the
Verilog & Blockdesign revisions,
everything seems to be in order, I am learning a lot by comparing the 2
design entry methods,
however I can’t find the top level Verlog Code for the CPLD/Atlas interface.
All I have here is another blockdesign?
 
What am I doing wrong? 
 
Kevin
M0KHZ
 
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