[hpsdr] JanusCPLD_Verilog code

[Christopher T. Day]

Kevin,

You're not doing anything wrong, I wimped out one that one. There is no
top-level Verilog file, at least not yet. It just looked too boring.
Maybe this weekend as I should catch up to more recent versions of Janus
anyway.

 

          Chris - AE6VK

 

 

  _____  

From: Gerda & Kevin [mailto:g5rda at tiscali.co.uk] 
Sent: Friday, February 16, 2007 12:02 PM
To: hpsdr at hpsdr.org
Subject: [hpsdr] JanusCPLD_Verilog code

 

Thanks guys, I'm having great fun!

As a budding 'hacker' I've been playing around with Quartus II and the
Janus code on the SVN.

 

This is probably a very stupid question but, after compiling both the
Verilog & Blockdesign revisions,

everything seems to be in order, I am learning a lot by comparing the 2
design entry methods,

however I can't find the top level Verlog Code for the CPLD/Atlas
interface.

All I have here is another blockdesign?

 

What am I doing wrong? 

 

Kevin

M0KHZ

 

 

 

 

 

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