[hpsdr] For budding firmware hackers...

[Malcolm Austin]

Chris,

Although I have subscribed to the HPSDR reflector for some months now, I'm very new to all this and have just been a lurker so far.

I have been trying to equip myself ready for Janus/Ozy to drop through the letterbox. I have two questions (which probably amount to the same thing): -

1. Where is the svn and what is it?
2. How do I get access to the code there?

Please excuse my ignorance but I haven't found any way to access it via my web browser and I am obviously missing some fundamental piece of info!

Malcolm Austin
  ----- Original Message ----- 
  From: Christopher T. Day 
  To: hpsdr at hpsdr.org 
  Sent: Wednesday, February 14, 2007 6:35 PM
  Subject: [hpsdr] For budding firmware hackers...


  ***** High Performance Software Defined Radio Discussion List *****




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  With the announcement of Janus and Ozy, I expect an increase in interest in programming the Janus CPLD and the Ozy FPGA; there are a lot of inveterate fiddlers on this list. You will need to gain some familiarity with Altera's Quartus II software to do this. Download at least the Quartus II Web Edition Software and the MegaCore IP Library from::

   

  < https://www.altera.com/support/software/download/altera_design/quartus_we/dnl-quartus_we.jsp >

   

  There is an _awful_ lot in there. As a beginner myself at this, I've only explored a tiny fraction of what's available. Start with the Help/Tutorial. This gives you a bare beginning, but doesn't take you very far. To make others' journeys a little easier and provide an example with a little more meat on it, I've refactored a snapshot of the Janus CPLD code and put it into SVN at:

   

  < svn://206.216.146.154/svn/repos_sdr_hpsdr/trunk/AE6VK/Janus/tags/Alpha2/1.0.0 >

   

  Download the code, and double-click on the Janus.qpf (Quartus Project File). While there is only one Project, there are two Revisions [Altera's term] in that project, a Block Design File revision and a Verilog revision. The Block Design File revision opens by default as I think it is easier to follow to start with. It is a form of direct schematic entry that nonetheless really compiles to loadable code. The Verilog revision is a traditional computer language format. To switch revisions, use the Project/Revisions. dialog and double-click on the other one.

   

  Since I've stored only the minimum source files, you will have to compile the code to get the full effect, once for each revision - use the Processing/Start Compilation menu item. Yes, I know there are a bunch of Warnings produced, but it's ok, believe me. Once the compilation is finished, you can expand the Hierarchy in the Project Navigator pane to see the structure of the code; double-click on a hierarchy element, and the corresponding source will open in the large Editor pane. I'm a hierarchy freak, so this is probably overdone, but it keeps each layer simple. 

   

  This is working code - it is running on my Janus/Ozy Alpha2 board set at the moment - but it is not final code, so it will need updates to work with the delivered boards. Happy exploring!

   

   

              Chris - AE6VK

   



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