[hpsdr] The Bit Budget?

[Chris Stratton]

I've been reading with interest about the HPSDR
project, and looked through most of the archives, and
am quite impressed by all of the work going on.  

One thing I am curious about though is what the known
limitations are that have been implicitly accepted in
trying to come up with practical implementations. 

Specifically, how does the selected/available
bit-width of various stages compare to what is
believed to be necessary for a first-class HF
communications receiver?
USRP certainly blazed a trail, but looks to be pretty
limited for any real use, but moving into the HPSDR
modules, and the Quick Silver project, how do the
capabilites of what is judged practical to build match
up to expected requirements?

The LTC2208 ADC at 16 bits seems to be with little
competition today, so at least in wideband
implementations that is a given - all one can do is
hope that processing gain overcomes its limitations.

What about NCO's - what kind of bit percision is
believed necessary in terms of phase input to the sine
function, and amplitude output?  Am I correct in
assuming people are going with CORDIC implementations
because lookup tables won't fit in non-BGA FPGA's? 
Anyone considered using an external memory for a
lookup table?

Or the digital down conversion - chips like the GC5016
or the AD6636 seem tempting, but at apparently only 16
bits output, would mean giving up on trying to get
processing gain.  In contemplated FPGA
implementations, what kinds of output bit widths back
up to the computer are folks shooting for?

Chris,
ex-N1IIR... might do something about that one of these days


 
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