[hpsdr] The Bit Budget?

[Philip Covington]

On 1/29/07, Chris Stratton <cs11102 at yahoo.com> wrote:
> ***** High Performance Software Defined Radio Discussion List *****
>
> I've been reading with interest about the HPSDR
> project, and looked through most of the archives, and
> am quite impressed by all of the work going on.
>
> One thing I am curious about though is what the known
> limitations are that have been implicitly accepted in
> trying to come up with practical implementations.
>
> Specifically, how does the selected/available
> bit-width of various stages compare to what is
> believed to be necessary for a first-class HF
> communications receiver?
> USRP certainly blazed a trail, but looks to be pretty
> limited for any real use, but moving into the HPSDR
> modules, and the Quick Silver project, how do the
> capabilites of what is judged practical to build match
> up to expected requirements?
>
> The LTC2208 ADC at 16 bits seems to be with little
> competition today, so at least in wideband
> implementations that is a given - all one can do is
> hope that processing gain overcomes its limitations.
>
> What about NCO's - what kind of bit percision is
> believed necessary in terms of phase input to the sine
> function, and amplitude output?  Am I correct in
> assuming people are going with CORDIC implementations
> because lookup tables won't fit in non-BGA FPGA's?
> Anyone considered using an external memory for a
> lookup table?
>
> Or the digital down conversion - chips like the GC5016
> or the AD6636 seem tempting, but at apparently only 16
> bits output, would mean giving up on trying to get
> processing gain.  In contemplated FPGA
> implementations, what kinds of output bit widths back
> up to the computer are folks shooting for?
>
> Chris,
> ex-N1IIR... might do something about that one of these days

Hello,

Right now I am maintaining a bit width of 32 bits in the DDC
implemented in the FPGA.  The maximum bit width in the CIC reaches 73
bits right now.  Each sample sent over USB consists of 8 bytes - 32
bits I and 32 bits Q.

I've taken two approaches with the DDC CIC filters.  One approach was
to use an 8-order decimate by 130 CIC with an internal bit width of 73
bits.  The other was to use prime number CIC decimation stages with a
3-order decimate by 13, 6-order decimate by 5, and 7-order decimate by
2.  Both are followed by a CIC compensation filter that does further
decimation.

The CORDIC based NCO uses a 32 bit accumulator and a width of 16 bits.
 Depending on how much room I have left in the EP2C8 FPGA, I will
expand the NCO's width.

It appears that we will probably go with a EP2C20 FPGA in the BGA
package to have enough room for the DDC.

73 de Phil N8VB

 1170170544.0