[hpsdr] 1pps

[Chris Bartram]

Phil

>  I've been doing some tests on various algorithms in
> an FPGA to lock my HP8640B to the 1PPS from a GPS receiver.  There seems to
> be plenty of options in terms of prior art but I started off with a very
> simple long term integration system. I started with a fast integration time
> and once in lock just keep on increasing the integration time.  For a KISS
> process it seems to work very well. I guess if this ever ends up as part of
> HPSDR since it's FPGA based then we can try many different algorithms over
> time.

The 1pps output is starting to be a thing of the past! More recent GPS 
receivers intended for timing applications are starting to acquire inbuilt 
NCOs which will allow synthesis of a FREQUENCY output from the receiver 
synchronously with the 1pps pulse. This simplifies things enormously, as it 
then becomes possible to move from the use of the frequency locked loop used 
in most existing designs to 'discipline' an external standard to GPS, to a 
phase locked loop. This allows the use of much larger loop bandwidths, and 
thus reduces the demands on the VCTCXO. 

Based on work work I did ~15years ago, I'm no great lover of FLLs!

As an example of a suitable GPS receiver look at the Navsync CW12-TIM. The 
current quoted 1off price from the UK distributor is ~100euro. The internal 
NCO will produce 1pps synchronous outputs up to 10MHz with very small jitter. 
You could even use a simple, cheap, integer-N synthesiser chip rather than an 
FPGA to lock a VCTCXO!! 

I wish I had the time to take this further in an amateur radio context.

Vy 73

Chris
GW4DGU