[hpsdr] Pandora Enclosure Project Proposal.

[Graham Haddock]

Lyle or Phil C:

What is the (approximate) power dissipation of one of the CPLD or FPGA 
devices
when used as a bus interface, and running at bus speed?

The smaller EPM240 as used on Janus?

The larger 208 pin FPGA device as used on Penelope and Ozy?

Just planning for the bus interface on ALEX.

Since these CPLD/FPGA devices are 3.3 volt, I assume then the
entire ATLAS bus is a 3.3 volt logic level bus?

Thanks,
--- Graham

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