[hpsdr] Pandora Enclosure Project Proposal.

[Lyle Johnson]

Hello Graham!

> What is the (approximate) power dissipation of one of the CPLD or FPGA 
> devices when used as a bus interface, and running at bus speed?

This is tough to answer.  It depends on the load on the bus (e.g., 
number and type of additional cards) and the number of lines being 
toggled (e.g., SPI toggling mostly 3 lines or some sort of parallel 
transfer toggling 16 or 32 or ??? lines).

> The smaller EPM240 as used on Janus?

The EPM240 draws little current when quiescent, and not much when 
running, say, a SPI interface.

> The larger 208 pin FPGA device as used on Penelope and Ozy?
>
Much higher quiescent current here.  The EPM240 has the equivalent of 
240 logic elements (LEs), while the FPGA has thousands of them.

Dynamic currents can vary over a very wide range.  This is an 
always-asked-seldom-answered-satisfactorily question about FPGAs. 
Altera has app notes on their web site to help calculate the power 
consumption.  In the end, you just have to measure it :-/

> Just planning for the bus interface on ALEX.

Alex will be mostly a receiver of data, I think.  Assuming it is updated 
infrequently - less than a few thousand times per second - the quiescent 
specs will dominate.  If you allow for say 2x the quiescent (nopt sleep 
or standby, if these are spec'ed differently) current you'll probably 
not be far off.

> Since these CPLD/FPGA devices are 3.3 volt, I assume then the
> entire ATLAS bus is a 3.3 volt logic level bus?

Yes, 3.3V is the interface level on the bus.

***

Looking over the latest Alex info on the wiki, I suspect the EPM240 
would easily handle these needs.  The I2C slave interface needs to be 
created to determine if it will fit in the logic fabric of the EPM240, 
though.  Digital Core Design claims their I2C slave core fits in a MAX 
II using only 75 LEs. < URL:http://www.fpga4fun.com/I2Cslave1.html > has 
example code for a simplified I2C slave. I haven't tried it, YMMV...

73,

Lyle KK7P


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