[hpsdr] Production Test Environment Up on SVN

[Scott Cowling]

Hi All,

I put up a (hopefully) complete copy of the test environment that we used 
for Janus and Ozy production.

It is on SVN under WA2DFI/Production_Setup.

Every directory contains a readme.txt file describing the functions of the 
files and sub-directories.

In the Docs directory is a PDF document that describes the test setups and 
the step-by-step procedure that we used to test each board.

In the Janus_CPLD directory you will find source and binaries for my Janus 
loopback test as well as Phil's production code. We loaded the loop-back 
test into the CPLD and verified that each board passed before loading 
Phil's production code. The production code is what is programmed into your 
Janus CPLD when you received it.

In the Ozy_FPGA directory you will find the Ozy loop-back test source and 
binaries for the Verilog code that Bill and I developed for Ozy testing. 
There is no production code here, as the FPGA is loaded from the FX2 with 
every boot. This allows you to have the latest Ozy FPGA code with the least 
hassle every time you boot up. You can find an FX2 loadable version of the 
Ozy FPGA firmware in the Working_Directory (see below).

In the Test_Fixture_Hardware directory are schematics (in both OrCAD and 
PDF for those without OrCAD) of the cables you will need to build to 
duplicate our test setups.

In the Working_Directory you will find all of the files that you will need 
to run all of the production tests. Just copy the entire directory to your 
Windows machine and open a command window in that directory and you should 
be able to run Bill's software loopback test. (Sorry Linux guys - I used 
W2K and XP Windoze machines for testing.)

We loaded the hardware loop-back test into the PROM on every Ozy board; you 
should be able to run it even if you do not have a ByteBlaster 
FPGA/CPLD/PROM programmer. Just move J24 from 1-2 to 2-3 to select Active 
Serial mode and the FPGA will load the loop-back test from the on-board 
PROM. Of course, you must build and install the loop-back cable on your 
ATLAS before you will be rewarded with the rotating LED pattern that proves 
that your board passes!.  Be sure to move J24 back to pins 1-2 (for Passive 
Serial mode) to allow the FX2 to load the FPGA for normal operation after 
you are done.

While this environment will not magically turn your Ozy/Janus/atlas into an
SDR overnight, I encourage you to read the documents, look at the Verilog 
code (we do have some comments for you to read :-), and learn as much as 
you can about the innards of your soon-to-be HPSDR rig.

It will help pass the time while we are waiting for Joe to finish the manuals.

I guess I should apologize on behalf of the test team for being so 
efficient in getting the boards all done so fast. :-) :-)

Anyway, have fun and let me know how it looks. I cranked a lot out pretty 
fast, so there are bound to be some mistakes.

73,
Scotty WA2DFI








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