[hpsdr] QSD gain and noise.

[Philip Covington]

On 9/24/07, Robert McGwier <rwmcgwier at gmail.com> wrote:
> I can't believe how many times this mistake is made.  I made it myself
> about four times.  I keep "rediscovering" this guaranteed source of
> jitter and phase noise.  The frequency will have to be an even divisor
> of the clock on you will have more spurs at sin(x)/x amplitudes than you
> can even believe.
>
> Bob
>
Yes, an interesting exercise is to connect the MSB of your accumulator
to one of the output pins on the FPGA - then look at what you get on a
spectrum analyzer when the divisor is not even - not very pretty :-)

73 Phil N8VB

 1190689980.0